1. Field of the Invention
This invention relates to a monolithic integrated high resolution charge balancing analog-to-digital converter.
2. Background Information
One previously known analog-to-digital converter architecture is the classical charge balancing analog-to-digital converter. This concept has a nonlinear relationship between the number of transitions in the feedback signal and the signal level. This is a disadvantage because the transition timing errors, resulting from the generation of the binary feedback signal, result in a nonlinear characteristic for the analog-to-digital converter.
For high resolutions, the time discrete signal must be evaluated during a large number of clock cycles. Consequently, the expected number of signal transitions also increases. This results in a limited achievable accuracy with the classical charge balancing analogue-to-digital converter architecture.